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After FRAMEN has been asserted, the data transfer proceeds normally. The PCI specification requires a Master to
assert IRDYN within eight clock cycles of FRAMEN assertion. For read transfers, this means that the backend must
provide data within eight clock cycles of DP_START being asserted. When RD_SYNC = 0 or RD_SYNC = 1, the
backend only has seven clock cycles to assert RD_STB_IN and meet the PCI latency requirements ( Figure 6-34 on
page 83 and Figure 6-35 ). For SX-A and RTSX-S implementations, this is reduced to six cycles. For write transfers, the
backend must assert WR_BE_NOW within eight clock cycles to meet the PCI requirements.
During the DMA startup period, the PCI arbiter may remove the bus grant before the core asserts FRAMEN. When
this occurs, the PCI core is required to terminate its DMA cycle. This is shown in Figure 6-37 on page 86 , where the
grant is removed after one cycle.
The core provides four additional input signals that are used to control DMA transfers: WR_BUSY_MASTER,
RD_BUSY_MASTER, STOP_MASTER, and STALL_MASTER. STOP_MASTER allows a DMA transfer in
progress to be stopped. WR_BUSY_MASTER and RD_BUSY_MASTER prevent DMA writes to and reads from the
backend from starting. STALL_MASTER allows slow backends to meet the FRAME-to-IRDY assertion requirement
for PCI.
cycle
A0
A1
A2
A3
0
1
2
3
4
5
6
7
8
9
clk
framen
cben[3:0]
7
0
ad[31:0]
ADDR
0
1
2
3
par
devseln
irdyn
trdyn
reqn
gntn
mast_active
dp_start
dp_done
bar_select[2:0]
rd_cyc
rd_stb_out
rd_stb_in
0
mem_add[11:0]
000
004
008 00C
010
014
018 01C
020
mem_data_in[31:0]
0
1
2
3
4
5
6
7
rd_sync
Figure 6-35 · DMA Burst Read Cycle (RD_SYNC = 1)
84
v4.0
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